Architecture, function interconnections, MAC PDU assembly, reset/re-establishment & 6G evolution
The MAC layer bridges RLC (above) and PHY (below), providing data transfer, scheduling, and control services. One MAC entity per cell group (MCG/SCG), managing up to 32 SCells.
Animated protocol stack showing data flow: SDAP → RLC → MAC (with all sub-functions) → PHY. Watch packets traverse the layers.
Data transfer (DL-SCH/UL-SCH), radio resource allocation, and MAC-internal control via CEs.
Logical channels (CCCH/DCCH/DTCH) map to transport channels (DL-SCH/UL-SCH/BCH/PCH/RACH).
Per cell group: 1 PCell + up to 32 SCells, 4 BWPs each. DC has 2 MAC entities (MCG + SCG).
MAC has 12 core functions that work together as an interconnected system. Each has a dedicated deep-dive page.
| # | Function | Purpose | Deep Dive |
|---|---|---|---|
| 1 | Scheduling | gNB decides who gets resources | Scheduling.md |
| 2 | LCP | Token-bucket grant filling | LCP.md |
| 3 | HARQ | Error correction via reTX | HARQ.md |
| 4 | BSR | Report buffer status to gNB | BSR.md |
| 5 | SR + RA Fallback | Request grants, fallback to RACH | SRAndRACHFallback.md |
| 6 | PHR | Report TX power margin | PHR.md |
| 7 | TA Maintenance | Keep UL timing aligned | TAMaintenance.md |
| 8 | DRX | Power-saving sleep cycles | DRX.md |
| 9 | Random Access | Initial access, RA fallback | UE-RACH-Procedure.md |
| 10 | CG / SPS | Pre-allocated periodic resources | SPSAndConfiguredGrants.md |
| 11 | DL Assignment | N1, preemption, priority | DLAssignmentHandling.md |
| 12 | Mux/Demux + Reset | PDU assembly, state cleanup | This page |
Every MAC transmission is a MAC PDU: a sequence of subPDUs, each containing a subheader (LCID + length) and a payload (MAC SDU, MAC CE, or padding).
Add MAC CEs and SDUs to build a MAC PDU. See subheaders, payload, and byte layout update in real-time.
| Subheader Field | Short (≤255B) | Long (>255B) |
|---|---|---|
| R (reserved) | 1 bit | 1 bit |
| F (format) | 0 (8-bit L) | 1 (16-bit L) |
| LCID | 6 bits | 6 bits |
| L (length) | 8 bits | 16 bits |
| Total | 2 bytes | 3 bytes |
Multiplexing (TX side): CEs first, then SDUs by LCP priority, then padding. Demultiplexing (RX side): parse subheaders → route CEs to MAC handlers, SDUs to RLC entities, discard padding.
Watch data from 3 logical channels plus MAC CEs get assembled into a single MAC PDU, step by step.
When the MAC entity is reset (RLF, handover, RRC reconfiguration), all state is cleared: HARQ buffers flushed, timers stopped, SPS/CG deactivated, SR/BSR/PHR cancelled.
Interactive visualization: populate MAC state, then trigger reset to see all state variables cleared one by one.
Clears MAC state only: HARQ, BSR, SR, PHR, TA, DRX, SPS/CG, SCells. RRC/RLC/PDCP unaffected.
MAC reset + RLC re-establishment + PDCP re-establishment. Triggered by RLF or handover failure.
UE performs RACH for new TA. First data triggers new BSR. SPS/CG must be re-activated by gNB.
| Issue | Symptom | Root Cause |
|---|---|---|
| Frequent MAC resets | DL/UL throughput drops | RLF / HO failure |
| Stale BSR after reset | gNB schedules wrong size | BSR not triggered |
| TA timer expiry | UL transmissions blocked | No TA MAC CE received |
| HARQ process exhaustion | Scheduling stalls | All 16 processes busy |
| Excessive padding | Wasted UL resources | Oversized grants |
| Aspect | LTE | 5G NR |
|---|---|---|
| Subheader | 2-3 bytes (fixed) | 2-3 bytes (flexible) |
| Max LCs | 11 | 33 |
| MAC CE types | ~10 | ~20+ |
| Max LCGs (BSR) | 4 | 8 |
| MAC entities | 1 per UE | 1 per cell group |
1-byte subheaders for common IoT packets (4-bit LCID + 4-bit L). 50% overhead reduction vs 5G NR.
AI predicts which LCs have data next TTI → pre-assembles PDU template → minimizes padding by 30-50%.
Direct memory references from RLC to PHY. No buffer copies. MAC latency < 50 μs (vs ~200 μs in 5G).
Compare MAC capabilities across generations: header size, LC count, CE types, assembly strategy, and processing latency.
| Dimension | 4G (LTE) | 5G NR | 6G (Target) |
|---|---|---|---|
| Subheader size | 2-3 bytes | 2-3 bytes | 1 byte |
| Max LCs | 11 | 33 | 64+ |
| MAC CE types | ~10 | ~20 | 30+ (AI-defined) |
| PDU assembly | Sequential | Sequential | AI-preassembled |
| Processing latency | ~1 ms | ~200 μs | < 50 μs |